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ASIC DESIGN FOR TEST ENGINEER - Acacia

extra holidays - fully flexible
Remote: 
Full Remote
Experience: 
Senior (5-10 years)
Work from: 

Offer summary

Qualifications:

BSEE with 8+ years or MSEE with 6+ years experience., PhD with 3+ years in ASIC DFT flows., Experience with Synopsys/Mentor DFT tools., Prior experience implementing scan control logic..

Key responsabilities:

  • Set up and implement MBIST, REPAIR, Boundary Scan.
  • Collaborate with RTL/PD/STA/ATE for successful tape out.

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Cisco Information Technology & Services XLarge http://www.cisco.com
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Job description

The application window is expected to close on 1/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.This role is within our ASIC team, specifically as part of the Design for Test group.

Your Impact

As a member of Acacia’s ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.

  • You will work with seasoned DFT engineers to implement and verify DFT.
  • You will also interact with RTL/PD/STA/ATE, collaborating with them for a successful tape out.

Minimum Qualification:

  • BSEE or equivalent with + 8 years of experience or an MSEE or equivalent with + 6 years of experience, or PHD with + 3 years of experience in ASIC DFT flows and Implementation
  • Prior experience implementing scan control logic in RTL
  • Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVT
  • Prior experience with Synopsys/Mentor DFT tools

Preferred Qualifications:

  • Experience with scan compression and scan partitioning
  • Experience with MemoryBIST, eFuse, Repair and yield improvement techniques
  • Experience with JTAG Boundary Scan Insertion AC/DC
  • Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
  • TCL scripting experience to automate DFT flows

#WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!

Required profile

Experience

Level of experience: Senior (5-10 years)
Industry :
Information Technology & Services
Spoken language(s):
English
Check out the description to know which languages are mandatory.

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