Offer summary

Qualifications:

Bachelor’s degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field., Five years of experience in analog layout design and physical verification., Proficiency in using Cadence or Synopsys tools for deep sub-micron CMOS technologies., Experience with advanced process nodes and high-speed I/O circuits..

Key responsibilities:

Perform physical layout designs for mixed-signal high-speed macro designs.

Collaborate closely with circuit designers across different countries.

Responsible for floor planning, custom layout, and verifying designs against rules and schematics.

Mentor junior layout engineers and prepare necessary documentation for tape-out.

Job description

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As an Analog Layout Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

Perform physical layout designs for mixed-signal high-speed macro designs. That includes RX, TX, ADC/DAC, PLL/DLL, Bandgap Voltage Reference, LDO, high-speed I/O circuits, general I/O's, ESD structures designs in deep sub-micron CMOS technologies using Cadence or Synopsys tools. Closely work with circuit designers across different countries. Responsible for floor planning, custom layout, and verifying against design rules and schematics, including DRC, LVS, ANT, LUP, ESD, and PERC. Prepare the waiver files and tape-out checklist. Mentor junior layout engineers. Wage $158,000.00 - $168,000.00 per year. Telecommuting is permitted.

What We're Looking For

Bachelor’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and five (5) years of experience in the job offered or related occupation.

Experience must include five (5) years with each of the following:
•   Developing layout schedules.
•   Advanced process nodes including N7, N5 and N3.
•   IP release and maintaining.
•   RX modules, PLL modules, TX modules.
•   Completing physical verification.
•   Performing floorplan and routing of analog/mixed-signal blocks and Ips.
•   ESD structures designs in deep sub-micron CMOS technologies.
•   Using Cadence or Synopsys tools.
•   High-speed I/O circuits.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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